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KS57C3204/p3204 product overview 1- 1 1 product overview overview the KS57C3204 single-chip cmos microcontroller has been designed for high perfo rmance using samsung's newest 4- bit cpu core, sam47 ( samsung arrangeable microcontrollers). with features such as lcd direct drive capability, 4-channel a/d converter, 24-bit am/fm frequency counter and watch timer , the KS57C3204 offers an excellent design solution for a wide variety of applications that require lcd functions and audio applications . up to 32 pins of the 64 -pin qfp package , it can be dedicated to i/o. five vectored interrupts provide fast response to internal and external events. in addition, the KS57C3204 's advanced cmos technology provides for low power consumption and a wide operat ing voltage range. otp the KS57C3204 microcontroller is also available in otp (one time programmable) version, ks57p3204 . the ks57p3204 microcontroller has an on-chip 4-kbyte one-time-programmable eprom instead of masked rom. the ks57p3204 is comparable to KS57C3204, both in function and in pin configuration.
product overview KS57C3204/p3204 1- 2 features memory ? 256 4-bit ram ? 4096 8-bit rom i/o pins ? input only: 8 pins ? i/o: 16 pins ? output only: 8 pins sharing with segment driver outputs lcd controller/driver ? maximum 14-digit lcd direct drive capability ? 28 segment and 4 common pins ? display modes: static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) ? internal resistor circuit for lcd bias 8-bit basic timer ? programmable interval timer ? watchdog timer 8-bit timer ? programmable 8-bit timer watch timer ? real-time and interval time measurement ? four frequency outputs to buz pin ? clock source generation for lcd 24-bit frequency counter (fc) ? level = 300mvpp (min.) ? amf input range = 0.5 mhz to 10 mhz ? fmf input range = 30 mhz to 150 mhz a/d converter ? 4-channels with 8-bit resolution ? 17 m s (min.) conversion speed bit sequential carrier ? support 16-bit serial data transfer in arbitrary format interrupts ? t wo internal vectored interrupts ? three external vectored interrupts ? two quasi-interrupts memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system clock stops) ? subsystem clock stops oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 k hz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.95, 1.91, 15.3 s at 4.19 mhz (main) ? 122 s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 1.8 v to 5.5 v at 3 mhz ? 3.0 v to 5.5 v at fc mode package type ? 64 -pin qfp
KS57C3204/p3204 product overview 1- 3 block diagram arithmetic and logic unit interrupt control block instruction register program counter program status word stack pointer instruction decoder internal interrupts c lock i/o port 1 input port 2 input port 3 a/d converter i/o port 4, 5 i/o port 6 256 x 4-bit data memory 4-kbyte program memory basic timer watch timer freq. counter 8-bit timer lcd driver/ countroller output port 8,9 p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int3 p2.0 p2.1 p2.2/fmf p2.3/amf p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 p4.0-p4.3 p5.0-p5.3 p6.0/buz p6.1/ks0 p6.2/ks1 p6.3/ks2 fmf com0-com3 amf seg0-seg19 p8.0-p8.3/ seg27-seg24 p9.0-p9.3/ seg23-seg20 reset x i n x out xt in xt out watchdog timer figure 1 -1 . KS57C3204 simplified block diagram
product overview KS57C3204/p3204 1- 4 pin assignments seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 p9.3/ seg20 p9.2/ seg21 p9.1/seg22 p9.0/ seg23 p8.3/ seg24 p8.2/ seg25 p8.1/seg26 p8.0/ seg27 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 KS57C3204 64-qfp (top view) p2. 0 p2.1 p2.2/fmf p2.3/amf p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3/adc3 v dd v ss x out x in test xt in xt out reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p4.0 p4.1 p4.2 p4.3 p5.0 p5.1 p5.2 p5.3 p6.0/buz p6.1/ks0 p6.2/ks1 p6.3/ks2 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 figure 1 -2 . KS57C3204 64- qfp pin assignment
KS57C3204/p3204 product overview 1- 5 pin descriptions table 1 - 1. KS57C3204 pin descriptions pin name pin type description number share pin reset value circuit type p1.0 p1.1 p1.2 p1.3 i /o 4-bit i/o port. 1-bit or 4-bit read, write, and test are possible. each pin can be specified as input or output port. pull-up resistors can be configured by software. 17 18 19 20 int0 int1 int2 int4 input d-4 p2.0 p2.1 p2.2 p2.3 i 4-bit input port. 1-bit and 4-bit read and test are possible. pull-up resistors can be configured by software. 1 2 3 4 ? ? fmf amf input a-4 a-4 b-4 b-4 p3.0 p3.1 p3.2 p3.3 i 4-bit input port. 1-bit and 4-bit read and test are possible pull-up resistors can be configured by software. 5 6 7 8 adc0 adc1 adc2 adc3 input f-13 p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o ports. n-channel open-drain output up to 5 v. 1-bit and 4-bit read, write, and test are possible. ports 4 and 5 can be paired to support 8-bit data. pull-up resistors can be configured by software. 21?24 25?28 ? ? input e-2 p6.0 p6.1 p6.2 p6.3 i/o 1-bit and 4-bit read, write, and test are possible. each pin can be specified as input or output port. pull-up resistors can be configured by software. 29 30 31 32 buz ks0 ks1 ks2 input d-2 d-4 d-4 d-4 seg0?seg19 o lcd segment signal output 60?41 ? output h-16 p8.0?p8.3 p9.0?p9.3 o 4-bit output ports. 1-bit and 4-bit write and test are possible. ports 8 and 9 can be paired to support 8-bit data. 33?36 37?40 seg27? seg20 output h-16 com0?com3 o lcd common signal output 64?61 ? output h-16 v dd ? main power supply 9 ? ? ? v ss ? main ground 10 ? ? ? x out , x in ? crystal, ceramic, or rc oscillator pins for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 11,12 ? ? ? xt out , xt in ? crystal oscillator pin for a subsystem clock. (for external clock input, use xt in and input xt in 's reverse phase to xt out ) 15,14 ? ? ?
product overview KS57C3204/p3204 1- 6 table 1 - 1. ks57p3204 pin descriptio ns (continued) pin name pin type description number share pin reset value circuit type seg20?seg27 o lcd s egment signal output 40?33 p9.0?p9.3 p8.0?p8.3 output h-16 adc0?adc3 i adc input ports 5?8 p3.0?p3.3 input f-13 fmf amf i external fm/am frequency inputs 3 4 p 2.2 p2.3 input b-4 int4 i external interrupt input with detection of rising or falling edges . 20 p1.3 input a-4 int2 i quasi-interrup t with detection of rising edge signals. 19 p1.2 input a-4 int1 int0 i external interrupt. the triggering edges for int0 and int1 are able to be selected. only int0 is synchronized with the system clock. 18 17 p1.1 p1.0 input a-4 buz o 2, 4, 8, or 16 k hz frequency output for buzzer sound with 4.19 mhz main system clock. 29 p6.0 input d-2 k s 0?k s2 i quasi-interrupt input with falling edge detection. 30?32 p6 . 1 ? p6 .3 input d-4 reset i system reset signal 16 ? input b test ? system test pin(must be connected to v ss) 13 ? ? ? note: pull-up resistors for all i/o ports automatically disabled if they are configured to output mode.
KS57C3204/p3204 product overview 1- 7 pin circuit diagrams v dd p-channel in n-chnnel figure 1 -3 . pin circuit type a v dd in pull-up enable figure 1 -4 . pin circuit type a-4 in v dd figure 1 -5 . pin circuit type b pull-down enable feedback enable type a figure 1 -6 . pin circuit type b-4
product overview KS57C3204/p3204 1- 8 v dd data output disable out figure 1 -7 . pin circuit type c pull-up enable data output disable i/o v dd circuit type c figure 1 -8 . pin circuit type d-2 pull-up enable data output disable i/o v dd circuit type c figure 1 -9 . pin circuit type d-4 data output disable v dd pne pull-up enable i/o v dd figure 1 -10 . pin circuit type e-2
KS57C3204/p3204 product overview 1- 9 v dd adcen in data to adc pull-up enable adc select figure 1 -11 . pin circuit type f-13
product overview KS57C3204/p3204 1- 10 v lc0 v lc1 seg/com and port data v lc2 v dd out figure 1 -12 . pin circuit type h-16
KS57C3204/p3204 electrical data 15- 1 15 electrical data overview in this section, information on KS57C3204 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? ab solute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data KS57C3204/p3204 15- 2 table 15-1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i n all i/o ports ? 0.3 to v dd + 0.3 output voltage v o ? ? 0.3 to v dd + 0.3 output current high i oh one i/o p ort active ? 15 ma all i/o ports active ? 30 output current low i ol one i/o port active + 30 (peak value) + 15 (note) total value for ports 1, 4, 5 and 6 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 note: the values for output current low ( i ol ) are calculated as peak value duty . table 15- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below 0.7 v dd ? v dd v v ih2 p1, p3, reset , p2.0 - 1 and p6.1 - 3 0.8 v dd v dd v ih3 x in , x out , xt in , and xt out v dd ? 0.1 v dd input l ow v oltage v il1 all input pins except those specified below ? ? 0.3 v dd v v il2 p1, p3, reset , p2.0 - 1 and p6.1 - 3 0.2 v dd v il3 x in , x out , xt in , and xt out 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 1 , 4, 5, and 6 v dd ? 1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v i oh = ?100 a port 8 and 9 v dd ? 2.0
KS57C3204/p3204 electrical data 15- 3 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v i ol = 1 5 ma , ports 1, 4, 5, and 6 ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v i ol = 100 m a ; ports 8and 9 ? ? 1 input h igh leakage c urrent (note) i lih1 v in = v dd all input pins ? ? 3 m a input low leakage c urrent (note) i lil1 v in = 0 v all input pins ? ? ? 3 output h igh l eakage c urrent (note) i loh 1 v out = v dd all output pins ? ? 3 output l ow l eakage c urrent (note) i lol v o ut = 0 v all output pins ? 3 pull-up r esistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 4, 5, and 6 20 40 80 k w v dd = 3 v 30 95 200 r l2 v in = 0 v; v dd = 5 v reset 100 230 400 v dd = 3 v 200 480 800 note: except for x in , x out , x t in , and x t out
electrical data KS57C3204/p3204 15- 4 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units lcd voltage dividing r esistor r lcd t a = 25 c 60 84 130 k w com output r com v dd = 5 v - 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v ? 3 6 impedance v dd = 3 v 5 15 com output voltage deviation v dc v dd = 5 v (v lc0 -comi) io = 15ua (i = 0?3) ? 45 90 mv seg output voltage deviation v ds v dd = 5 v (v lc0 -segi) io = 15ua (i = 0?27) ? 45 90 oscillator feedback resistor r osc1 v dd = 5. 0 v; t a = 25; x in = v dd , x out = 0 v 300 600 1500 k w r osc2 v dd = 5. 0 v; t a = 25; xt in = v dd , xt out = 0 v 1230 2630 4000
KS57C3204/p3204 electrical data 15- 5 table 15- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd 1 main operating: fc enable pcon = 0011b, scmod = 0000b crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.19 mhz ? 5.2 10 ma i dd 2 (2) main operating: 6.0 mhz ? 3.5 8 pcon = 0011b, scmod = 0000b crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.19 mhz 2.5 5.5 v dd = 3 v 10% 6.0 mhz 1.6 4 4.19 mhz 1.2 3 i dd 3 ( 2 ) main i dle mode (3) : 6.0 mhz ? 1.0 2.5 pcon = 0111b, scmod =0000b c rystal oscillator c1 = c2 = 22 pf v dd = 5 v 10 % 4.19 mhz 0.9 2.0 v dd = 3 v 10% 6.0 mhz 0.5 1.0 4.19 mhz 0.4 0.8 i dd 4 (2) sub operating mode: pcon = 0011b, scmod = 1001b v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 ua i dd 5 (2) sub i dle mode: pcon = 0111b, scmod = 1001b v dd = 3 v 10% 32 khz crystal oscillator ? 6 15 i dd6 (2) stop mode: cpu = fxt/4, scmod = 1101b v dd = 5 v 10% ? 0.5 3 i dd 7 (2) stop mode: cpu = fx/4, scmod = 0100b v dd = 5 v 10% ? notes: 1. supply current does not include current drawn through internal pull-up resistors and lcd voltage dividing resistors. 2. amf or fmf is a normal input mode. 3 . data includes the power consumption for sub - system clock oscillation.
electrical data KS57C3204/p3204 15- 6 table 15- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator c1 c2 x in x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 2.7 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 2.7 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator r x in x out frequency (1) v dd = 5 v r = 15 k w , v dd = 5 v r = 25 k w , v dd = 3 v 0.4 - 2.0 1.0 2.5 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
KS57C3204/p3204 electrical data 15- 7 table 15- 4. subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in xt out c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 2.7 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 k hz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs.
electrical data KS57C3204/p3204 15- 8 table 15-5 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f clk = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf table 15-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 1.3 64 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, int4, k s 0 ? k s2 10 reset input low width t rsl input 10 ? ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx x as assigned by the imod0 register setting. table 15-6 . a.c. electrical characteristics ( continued) (t a = ? 1 0 c to + 70 c, v dd = 3.5 v to 5 . 5 v) parameter symbol conditions min typ max units a/d converting resolution ? ? 8 8 8 bits absolute accuracy ? ? ? ? 2 lsb ad conversion time t con ? 17 34/fxx (note) ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 1000 ? m w note: fxx stands for the system clock ( fx or fxt).
KS57C3204/p3204 electrical data 15- 9 table 15-6 . a.c. electrical characteristics ( continued) (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5 . 5 v) parameter symbol conditions min typ max units input voltage (peak to peak) v in amf/fmf mode, sine wave input 0.3 ? v dd v frequency f amf amf mode, sine wave input; v in = 300mv p-p 0.5 ? 10 mhz f fmf fmf mode, sine wave input; v in = 300mv p-p 30 150 cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1 supply voltage (v) 250 khz 500 khz 15.6 khz cpu clock 750 khz 1.0475 mhz 1.5 mhz 2 3 4 5 6 7 main osc. freq. 3 mhz 4.19 mhz 6 mhz 40 0 khz when fc operates, operating voltage range is 3.0 v to 5.5 v. figure 15- 1. standard operating voltage range table 15-7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 1 m a
electrical data KS57C3204/p3204 15- 10 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 15- 2. stop mode release timing when initiated b y reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 15- 3. stop mode release timing when initiated b y an interrupt request
KS57C3204/p3204 electrical data 15- 11 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 15- 4. a.c. timing measurement points (except for x in and xt in ) x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 15- 5. clock timing measurement at x in xt in t xtl t xth 1 / f xt v dd ? 0.1 v 0.1 v figure 15- 6. clock timing measurement at xt in
electrical data KS57C3204/p3204 15- 12 reset t rsl 0.2 v dd figure 15-7 . input timing for reset signal int0, 1, 2, 4 ks0 to ks2 t intl t inth 0.8 v dd 0.2 v dd figure 15-8 . input timing for external interrupts and quasi-interrupts
KS57C3204/p3204 mechanical data 16-1 16 mechanical data overview the KS57C3204 microcontroller is available in a 64 -pin qf p package ( samsung: 64-qfp-1420f). package dimensions are shown in figure 16-1. note : dimensions are in millimeters. 17.90 0.3 14.00 0.2 (1.00 ) 64-qfp-1420f 23.90 0.3 #64 (1.00) #1 0.40 +0.10 - 0.05 0.15max 0.80 0.20 2.65 0.10 0.05~0.25 3.00 max 0.15 +0.10 - 0.05 0-8 0.10 max 0.80 0.20 1.00 20.0 0 0.2 figure 16-1. 64 -qfp-14 20f package dimensions
mechanical data KS57C3204/p3204 16 ? 2 notes
KS57C3204/p3204 ks5 7p3204 otp 17- 1 1 7 ks57p3204 otp overview the ks57p3204 single-chip cmos microcontroller is the otp (one time programmable) version of the KS57C3204microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the ks57p3204 is fully compatible with the KS57C3204, both in function and in pin configuration. because of its simple programming requirements, the ks57p3204 is ideal for use as an evaluation chip for the KS57C3204.
ks57p3204 otp KS57C3204/p3204 17- 2 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 p9.3/ seg20 p9.2/ seg21 p9.1/seg22 p9.0/ seg23 p8.3/ seg24 p8.2/ seg25 p8.1/seg26 p8.0/ seg27 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ks57p3204 64-qfp (top view) p2. 0 p2.1 p2.2/fmf p2.3/amf p3.0/adc0 p3.1/adc1 sdat / p3.2/adc2 sclk /p3.3/adc3 v dd / v dd v ss /v ss x out x in v pp /test xt in xt out reset / reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p4.0 p4.1 p4.2 p4.3 p5.0 p5.1 p5.2 p5.3 p6.0/buz p6.1/ks0 p6.2/ks1 p6.3/ks2 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 figure 17-1. ks57p3204 pin assignments (64-qfp)
KS57C3204/p3204 ks5 7p3204 otp 17- 3 table 17-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.2 sdat 7 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input or push-pull output port. p3.3 sclk 8 i/o serial clock pin. input only pin. test v pp (test) 13 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. reset reset 16 i chip initialization v dd / v ss v dd / v ss 9/10 i logic power supply pin. v dd should be tied to +5 v during programming. table 17-2. comparison of ks57p3204 and KS57C3204 features characteristic ks57p3204 KS57C3204 program memory 4k bytes eprom 4k bytes mask rom operating voltage (v dd ) 2.0 v to 5.5 v at 4.19 mhz 1.8 v to 5.5 v at 3 mhz 2.0 v to 5.5 v at 4.19 mhz 1.8 v to 5.5 v at 3 mhz otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 64 qfp 64 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the vpp (test) pin of the ks57p3204, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 17-3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
ks57p3204 otp KS57C3204/p3204 17- 4 table 17-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below 0.7 v dd ? v dd v v ih2 p1, p3, reset , p2.0 - 1 and p6.1 - 3 0.8 v dd v dd v ih3 x in , x out , xt in , and xt out v dd ? 0.1 v dd input l ow v oltage v il1 all input pins except those specified below ? ? 0.3 v dd v v il2 p1, p3, reset , p2.0 - 1 and p6.1 - 3 0.2 v dd v il3 x in , x out , xt in , and xt out 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 1 , 4, 5, and 6 v dd ? 1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v i oh = ?100 a port 8 and 9 v dd ? 2.0
KS57C3204/p3204 ks5 7p3204 otp 17- 5 table 17-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v i ol = 1 5 ma , ports 1, 4, 5, and 6 ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v i ol = 100 m a ; ports 8 and 9 ? ? 1 input h igh leakage c urrent (note) i lih1 v in = v dd all input pins ? ? 3 m a input low leakage c urrent (note) i lil1 v in = 0 v all input pins ? ? ? 3 output h igh l eakage c urrent (note) i loh 1 v out = v dd all output pins ? ? 3 output l ow l eakage c urrent (note) i lol v o ut = 0 v all output pins ? ? ? 3 pull-up r esistor r l1 v in = 0 v; v dd = 5 v ports 1, 2, 3, 4, 5, and 6 20 40 80 k w v dd = 3 v 30 95 200 r l2 v in = 0 v; v dd = 5 v reset 100 230 400 v dd = 3 v 200 480 800 note: except for x in , x out , x t in , and x t out
ks57p3204 otp KS57C3204/p3204 17- 6 table 17-4 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units lcd voltage dividing r esistor r lcd t a = 25 c 60 84 130 k w com output r com v dd = 5 v - 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v ? 3 6 impedance v dd = 3 v 5 15 com output voltage deviation v dc v dd = 5 v (v lc0 -comi) io = 15ua (i = 0?3) ? 45 90 mv seg output voltage deviation v ds v dd = 5 v (v lc0 -segi) io = 15ua (i = 0?27) ? 45 90 oscillator feedback resistor r osc1 v dd = 5. 0 v; t a = 25; x in = v dd , x out = 0 v 300 600 1500 k w r osc2 v dd = 5. 0 v; t a = 25; xt in = v dd , xt out = 0 v 1230 2630 4000
KS57C3204/p3204 ks5 7p3204 otp 17- 7 table 17-4 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (1) i dd 1 main operating: fc enable pcon = 0011b, scmod = 0000b crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.19 mhz ? 5.2 10 ma i dd 2 (2) main operating: 6.0 mhz ? 3.5 8 pcon = 0011b, scmod = 0000b crystal oscillator c1 = c2 = 22 p f v dd = 5 v 10 % 4.19 mhz 2.5 5.5 v dd = 3 v 10% 6.0 mhz 1.6 4 4.19 mhz 1.2 3 i dd 3 ( 2 ) main i dle mode (3) : 6.0 mhz ? 1.0 2.5 pcon = 0111b, scmod =0000b c rystal oscillator c1 = c2 = 22 pf v dd = 5 v 10 % 4.19 mhz 0.9 2.0 v dd = 3 v 10% 6.0 mhz 0.5 1.0 4.19 mhz 0.4 0.8 i dd 4 (2) sub operating mode: pcon = 0011b, scmod = 1001b v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 ua i dd 5 (2) sub i dle mode: pcon = 0111b, scmod = 1001b v dd = 3 v 10% 32 khz crystal oscillator ? 6 15 i dd6 (2) stop mode: cpu = fxt/4, scmod = 1101b v dd = 5 v 10% ? 0.5 3 i dd 7 (2) stop mode: cpu = fx/4, scmod = 0100b v dd = 5 v 10% ? notes: 1. supply current does not include current drawn through internal pull-up resistors and lcd voltage dividing resistors. 2. amf or fmf is a normal input mode. 3 . data includes the power consumption for sub - system clock oscillation.
ks57p3204 otp KS57C3204/p3204 17- 8 table 17-5 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator c1 c2 x in x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 2.7 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 2.7 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator r x in x out frequency (1) v dd = 5 v r = 15 k w , v dd = 5 v r = 25 k w , v dd = 3 v 0.4 - 2.0 1.0 2.5 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
KS57C3204/p3204 ks5 7p3204 otp 17- 9 table 17-6 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in xt out c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 2.7 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 k hz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs.
ks57p3204 otp KS57C3204/p3204 17- 10 table 17-7 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f clk = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf table 17-8 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 1.3 64 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, int4, k s 0 ? k s2 10 reset input low width t rsl input 10 ? ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock/4 (fx/4) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx x as assigned by the imod0 register setting. table 17-8 . a.c. electrical characteristics ( continued) (t a = ? 1 0 c to + 70 c, v dd = 3.5 v to 5 . 5 v) parameter symbol conditions min typ max units a/d converting resolution ? ? 8 8 8 bits absolute accuracy ? ? ? ? 2 lsb ad conversion time t con ? 17 34/fxx (note) ? m s analog input voltage v ian ? v ss ? v dd v analog input impedance r an ? 2 1000 ? m w note: fxx stands for the system clock ( fx or fxt).
KS57C3204/p3204 ks5 7p3204 otp 17- 11 table 17-8 . a.c. electrical characteristics ( continued) (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5 . 5 v) parameter symbol conditions min typ max units input voltage (peak to peak) v in amf/fmf mode, sine wave input 0.3 ? v dd v frequency f amf amf mode, sine wave input; v in = 300mv p-p 0.5 ? 10 mhz f fmf fmf mode, sine wave input; v in = 300mv p-p 30 150 cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1 supply voltage (v) 250 khz 500 khz 15.6 khz cpu clock 750 khz 1.0475 mhz 1.5 mhz 2 3 4 5 6 7 main osc. freq. 3 mhz 4.19 mhz 6 mhz 40 0 khz when fc operates, operating voltage range is 3.0 v to 5.5 v. figure 17-2 . standard operating voltage range table 17-9 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 1 m a
ks57p3204 otp KS57C3204/p3204 17- 12 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 17-3 . stop mode release timing when initiated b y reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 17-4 . stop mode release timing when initiated b y an interrupt request
KS57C3204/p3204 ks5 7p3204 otp 17- 13 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 17-5 . a.c. timing measurement points (except for x in and xt in ) x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 17-6 . clock timing measurement at x in xt in t xtl t xth 1 / f xt v dd ? 0.1 v 0.1 v figure 17-7 . clock timing measurement at xt in
ks57p3204 otp KS57C3204/p3204 17- 14 reset t rsl 0.2 v dd figure 17-8 . input timing for reset signal int0, 1, 2, 4 ks0 to ks2 t intl t inth 0.8 v dd 0.2 v dd figure 17-9 . input timing for external interrupts and quasi-interrupts

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